HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 264

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Exception Handling
An Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or
some exception will be retained to prevent an exception acceptance at an instruction where
returning from the exception cannot be performed correctly. For details, refer to repeat loop
program example 1 to 4. In the examples, exceptions generated at instructions indicated as [B],
[C], [C1], or [C2], the following processing is executed.
• Interrupt, DMA address error
Note: * An interrupt request or a DMA address error exception request is retained in the
• User break before instruction execution
• User break after instruction execution
Table 9.5
Rev. 4.00 Sep. 14, 2005 Page 214 of 982
REJ09B0023-0400
Exception Type
Interrupt
DMA address error
User break before instruction execution
User break after instruction execution
An exception request is not accepted and retained at instructions [B] and [C]. If an instruction
indicates as [A] is executed the next time, an exception request is accepted.* As shown in
example 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat loop
consisting of four instructions or less.
A user break before instruction execution is accepted at instruction [B], and an address of
instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but
the exception request is retained until an instruction [A] or [B] is executed the next time. Then,
the exception request is accepted before an instruction [A] or [B] is executed. In this case, an
address of instruction [A] or [B] is saved in the SPC.
A user break after instruction execution cannot be accepted at instructions [B] and [C] but the
exception request is retained until an instruction [A] or [B] is executed the next time. Then, the
exception request is accepted before an instruction [A] or [B] is executed. In this case, an
address of instruction [A] or [B] is saved in the SPC.
interrupt controller (INTC) and the direct memory access controller (DMAC) until the
CPU can accept a request.
Exception Acceptance in the Repeat Loop
Instruction [B]
Not accepted
Not accepted
Accepted
Not accepted
Instruction [C]
Not accepted
Not accepted
Not accepted
Not accepted