HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 445

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes:
CSnBCR
Idle
Setting
4
4
4
4
4
4
4
4
n (n>=6) 
BSC Register Setting
1. DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
CS3WCR.
WTRP
Setting
2
2
2
2
3
3
3
3
The minimum number of idle cycles in CPU Access is described sequentially for Iφ:Bφ
(4:1/3:1/2:1/1:1).
changing a clock ratio.
CS3WCR.
TRWL
Setting
0
1
2
3
0
1
2
3

Read to
Read
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
All n+1
Write to
Write
4/4/4/4
4/4/4/4
4/4/4/4
5/5/5/5
4/4/4/4
4/4/4/4
5/5/5/5
6/6/6/6
n/n/n/n
CPU Access
Read to
Write
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
5/5/5/5
All n+1
Rev. 4.00 Sep. 14, 2005 Page 395 of 982
Section 12 Bus State Controller (BSC)
Write to
Read
4/4/4/4
4/4/4/4
4/4/4/4
5/5/5/5
4/4/4/4
4/4/4/4
5/5/5/5
6/6/6/6
n/n/n/n
Read to
Write
5
5
5
5
5
5
5
5
n+1
DMAC Access
REJ09B0023-0400
Write to
Read
4
4
4
5
4
4
5
6
n