HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 346

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 296 of 982
REJ09B0023-0400
Bit
12
11
10
9
8
7
6
Bit Name
SW1
SW0
WR3
WR2
WR1
WR0
WM
Initial
Value
0
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Number of Delay Cycles from Address, CSn Assertion
to RD, WE Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Number of Read Access Wait Cycles
Specify the number of cycles that are necessary for
read access.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Reserved (Setting prohibited)
External Wait Mask Specification
Specifies whether or not the external wait input is
valid. The specification by this bit is valid even when
the number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored