HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 998

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 948 of 982
REJ09B0023-0400
A12/A11*
D31 to D0
A25 to A0
DACKn*
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
RASU/L
CASU/L
RD/WR
DQMxx
Figure 25.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
CKIO
CKE
CSn
BS
1
2
Note:
t
t
t
t
t
t
DQMD1
AD1
RASD1
DACD
t
CSD1
RWD1
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
AD1
Tp
t
t
WTRCD = 0 Cycle, TRWL = 0 Cycle)
RWD1
RASD1
Row address
t
AD1
Tpw
t
RASD1
Tr
t
t
t
t
t
RWD1
RASD1
t
t
BSD
WDD2
AD1
CASD1
AD1
Tc1
(High)
t
t
WDH2
AD1
Tc2
Column
address
Writecommand
t
AD1
Tc3
t
t
AD1
WDD2
Tc4
t
t
DQMD1
t
t
t
t
t
t
BSD
t
DACD
AD1
CSD1
CASD1
WDH2
AD1
RWD1