HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 45

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 7.8
Section 8 X/Y Memory
Table 8.1
Section 9 Exception Handling
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Section 10 Interrupt Controller (INTC)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Section 11 User Break Controller (UBC)
Table 11.1
Table 11.2
Table 11.3
Section 12 Bus State Controller (BSC)
Table 12.1
Table 12.2
Table 12.3
Table 12.4
Table 12.5
Table 12.6
Table 12.7
Table 12.8
Table 12.8
Table 12.9
Table 12.9
When a Memory Access Exception Occurs in Repeat Control............................. 215
Address Multiplex Output (1)-1............................................................................ 340
Address Multiplex Output (1)-2............................................................................ 341
Address Multiplex Output (2)-1............................................................................ 342
Address Multiplex Output (2)-2............................................................................ 343
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1)............... 186
X/Y Memory Specifications ................................................................................. 193
Exception Event Vectors....................................................................................... 204
Type of Reset........................................................................................................ 206
Instruction Positions and Restriction Types.......................................................... 210
SPC Value When a Re-Execution Type Exception Occurs in Repeat Control ..... 213
Exception Acceptance in the Repeat Loop ........................................................... 214
Instruction Where a Specific Exception Occurs
Pin Configuration.................................................................................................. 221
Interrupt Sources and IPRB to IPRJ ..................................................................... 224
Correspondence between Interrupt Sources and IMR0 to IMR10 ........................ 230
Correspondence between Interrupt Sources and IMCR0 to IMCR10................... 232
Interrupt Exception Handling Sources and Priority .............................................. 236
Specifying Break Address Register ...................................................................... 246
Specifying Break Data Register............................................................................ 248
Data Access Cycle Addresses and Operand Size Comparison Conditions ........... 258
Pin Configuration.................................................................................................. 272
Address Space Map 1 (CMNCR.MAP = 0).......................................................... 275
Address Space Map 2 (CMNCR.MAP = 1).......................................................... 276
Correspondence between External Pin MD3 and Bus Width of Area 0 ............... 277
32-Bit External Device Access and Data Alignment ............................................ 321
16-Bit External Device Access and Data Alignment ............................................ 322
8-Bit External Device Access and Data Alignment .............................................. 323
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Relationship between BSZ1, 0, A2/3ROW1, 0, and
Rev. 4.00 Sep. 14, 2005 Page xlv of l