HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 234

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Cache
Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
Rev. 4.00 Sep. 14, 2005 Page 184 of 982
REJ09B0023-0400
Bit
31 to 17
16
15 to 10
9
8
7 to 2
1
0
Bit Name

LE

W3LOAD
W3LOCK

W2LOAD
W2LOCK
Initial
value
All 0
0
All 0
0
0
All 0
0
0
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Lock Enable
This bit enables or disables the cache locking function.
0: Cache locking mode is entered when SR.DSP=1
1: Cache locking mode is entered regardless of the
Reserved
These bits are always read as 0. The write value
should always be 0.
Way 3 Load
Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the prefetched data is loaded into the
way to which LRU points.
Reserved
These bits are always read as 0. The write value
should always be 0.
Way 2 Load
Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the prefetched data is loaded into the
way to which LRU points.
value of SR.DSP