HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 795

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Where: M: Receive margin (%)
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Synchronization
sampling timing
Data sampling
Receive data
M = (0.5 -
Base clock
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
= (0.5 – 1/(2 × 16)) × 100%
= 46.875%
Figure 19.19 Receive Data Sampling Timing in Asynchronous Mode
timing
(RxD)
2N
0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5
1
) = (L - 0.5) F -
Start bit
8 clocks
16 clocks
–7.5 clocks
D - 0.5
N
Section 19 Serial Communication Interface with FIFO (SCIF)
(1+F) × 100 %
+7.5 clocks
Rev. 4.00 Sep. 14, 2005 Page 745 of 982
D0
REJ09B0023-0400
D1