HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 248

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Exception Handling
9.1
There are three registers for exception handling. A register with an undefined initial value should
be initialized by the software.
• TRAPA exception register (TRA)
• Exception event register (EXPEVT)
• Interrupt event register 2 (INTEVT2)
Figure 9.1 shows the bit configuration of each register.
9.1.1
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Rev. 4.00 Sep. 14, 2005 Page 198 of 982
REJ09B0023-0400
Bit
31 to 10
9 to 2
1, 0
Register Descriptions
TRAPA Exception Register (TRA)
Bit Name

TRA

31
31
31
Initial
Value



Figure 9.1 Register Bit Configuration
0
0
0
R/W
R
R/W
R
12 11
12 11
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-Bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0.
10 9
EXPEVT
INTEVT2
TRA
2 1 0
0
0
0
TRA
EXPEVT
INTEVT2