HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 414

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Auto-
refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in
SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If
synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power
consumption for data retention is low, can be activated by setting both the RMODE bit and the
RFSH bit to 1.
Rev. 4.00 Sep. 14, 2005 Page 364 of 982
REJ09B0023-0400
RASL, RASU
CASL, CASU
(Bank Active, Different Row Addresses in the Same Bank)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CSn
BS
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
Figure 12.28 Single Write Timing
2. The waveform for DACKn is when active low is specified.
Tp
Tpw
Tr
Tc1