HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 438

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
6. Data output from an external device caused by DMA single address transfer is followed by
7. Data output from an external device caused by DMA single address transfer is followed by any
Besides the wait cycles between access cycles (idle cycles) described above, idle cycles must be
inserted to reserve the minimum pulse width for an interface with an internal bus and a
multiplexed pin (WEn).
8. Idle cycle of the external bus for the interface with the internal bus
9. Idle cycle of the external bus for accessing different memory
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data output from another device that includes this LSI (DMAIWA = 0)
For details, see the description of the DMAIWA bit in the CMNCR register.
type of access (DMAIWA = 1)
A. Insert one idle cycle immediately before a write access cycle after an external bus idle
B. Insert one idle cycle to transfer the read data to the internal bus when a read cycle of the
For accessing different memory, insert idle cycles as follows. The byte-selection SRAM
interface with the BAS bit = 1 specified is handled as an SDRAM interface because the WEn
change timing is identical.
A. Insert one idle cycle to access the interface other than the SDRAM interface after the write
B. Insert one idle cycle to access the SDRAM interface after the normal space interface with
C. Insert one idle cycle to access the SDRAM interface after the MPX-IO interface is
D. Insert one idle cycle to access the MPX-IO interface from the external bus that is in the idle
E. Insert one idle cycle to access the MPX-IO interface after a read cycle is performed in the
F. Insert two idle cycles to access the MPX-IO interface after a write cycle is performed in the
G. Insert one idle cycle to access the SDRAM interface which is not in the low frequency
cycle or a read cycle.
external bus terminates.
Insert two to three idle cycles including the idle cycle in A. for the write cycle immediately
after a read cycle.
access cycle is performed in the SDRAM interface.
the external wait invalidated or the byte-selection SRAM interface with the BAS bit = 0
specified is accessed.
accessed.
status.
normal space interface, byte-selection SRAM interface with the BAS bit = 0 specified or
the SDRAM interface.
SDRAM interface.
mode after the interface in the SDRAM low frequency mode (SDCR.SLOW = 1) is
accessed.