HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 551

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

16.4.7
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 16.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the system clock. When NF2CYC is set to 0, this signal is not passed forward
to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this signal is
not passed forward to the next circuit unless the outputs of three latches agree. If they do not
agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
Noise Filter
Sampling clock
D
Peripheral clock
Latch
C
cycle
Figure 16.17 Block Diagram of Noise Filter
Q
D
Latch
C
Q
D
Latch
C
NF2CVC
Q
Rev. 4.00 Sep. 14, 2005 Page 501 of 982
Section 16 I
detector
detector
Match
Match
2
C Bus Interface 2 (IIC2)
1
0
REJ09B0023-0400
SCL or SDA
Internal
signal