HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 440

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
Table 12.19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual
Notes:
Rev. 4.00 Sep. 14, 2005 Page 390 of 982
REJ09B0023-0400
BSC Register Setting
CSnWCR.
WM Setting
1
0
1
0
1
0
1
0
0, 1
1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the
2. Minimum number of idle cycles for other than the above cases.
DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
32-bit access cycle when the bus width is 16 bits, and the minimum number of idle
cycles between continuous access cycles during 16-byte transfer
CSnBCR
Idle Setting
0
0
1
1
2
2
4
4
n (n≥6)
Address Mode Transfer for the Normal Space Interface
Read to
Write
2
2
2
2
2
2
4
4
n
When Access Size is
Less than Bus Width
Write to
Read
0
1
1
1
2
2
4
4
n
Continuous
Read*
0
1
1
1
2
2
4
4
n
When Access Size Exceeds Bus Width
1
Read to
Write*
2
2
2
2
2
2
4
4
n
2
Continuous
Write*
0
1
1
1
2
2
4
4
n
1
Write to
Read*
0
1
1
1
2
2
4
4
n
2