HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 120

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Rev. 4.00 Sep. 14, 2005 Page 70 of 982
REJ09B0023-0400
Instruction
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
OP:
Sz:
SRC:
DEST: Destination
Destination register
2. Scaled (×1, ×2, or ×4) according to the instruction operand size, etc.
Operation code
Size
Source
(1)
(2)
instruction execution states will be increased in cases such as the following:
When there is contention between an instruction fetch and a data access
When the destination register of a load instruction (memory → register) is also
used by the following instruction
Instruction Code
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd: Displacement*
0000: R0
0001: R1
.........
1111: R15
Immediate data
2
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx):
M/Q/T: Flag bits in SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive logical OR of
~: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
each bit
Memory operand
Execution States
Value
when no wait states
are inserted*
1
T Bit
Value of T bit
after instruction
is executed
Explanation of
Symbols
—: No change