HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 529

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.2
ICCR2 is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA
pin, monitors the SCL pin, and controls reset in the control part of the I
Bit
7
6
5
I
2
Bit Name
BBSY
SCP
SDAO
C Bus Control Register 2 (ICCR2)
Initial
Value
0
1
1
R/W
R/W
W
R/W
Description
Bus Busy
This bit enables to confirm whether the I
occupied or released and to issue start/stop conditions
in master mode. With the clocked synchronous serial
format, this bit has no meaning. With the I
this bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low to
high under the condition of SCL = high, assuming that
the stop condition has been issued. Write 1 to BBSY
and 0 to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start condition.
Write 0 in BBSY and 0 in SCP to issue a stop condition.
Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1.
SDA Output Value Control
This bit is used with SDAOP when modifying output
level of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output low.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
Rev. 4.00 Sep. 14, 2005 Page 479 of 982
Section 16 I
2
C bus interface 2.
2
C Bus Interface 2 (IIC2)
REJ09B0023-0400
2
C bus is
2
C bus format,