HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 98

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.4
2.4.1
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.11 Addressing Modes and Effective Addresses for CPU Instructions
Rev. 4.00 Sep. 14, 2005 Page 48 of 982
REJ09B0023-0400
Addressing
Mode
Register direct
Register indirect @Rn
Register
indirect with
post-increment
Register
indirect with
pre-decrement
Instruction Formats
CPU Instruction Addressing Modes
Instruction
Format
Rn
@Rn+
@–Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Effective address is register Rn contents. It is
decremented by a constant beforehand: 1 for
a byte operand, 2 for a word operand, 4 for
a longword operand.
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rn
Rn
Calculation Formula

Rn
Rn
After instruction execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 → Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with Rn
after calculation)