HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 288

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Interrupt Controller (INTC)
10.5
10.5.1
The sequence of interrupt operations is described below. Figure 10.2 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
5. The interrupt source code is set in the interrupt event register (INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL) and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by
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following the priority levels set in interrupt priority registers B to J (IPRB to IPRJ). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest priority is
selected, according to table 10.5.
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
synchronization with the peripheral clock (Pφ). The CPU receives an interrupt at a break in
instructions.
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT2 register value as its offset in order to identify the
interrupt source. This enables it to branch to the handling routine for the individual interrupt
source.
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
INTC Operation
Interrupt Sequence
acceptance of an interrupt in this LSI.
interrupt request that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, and then execute an RTE instruction.