HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 493

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to
an 8-bit external device, the DACK and TEND outputs are divided for data alignment as shown in
figure 13.18.
Write
Read
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Figure 13.18 BSC Ordinary Memory Access
(Active low)
(Active low)
Note: TEND is asserted for the last transfer unit of DMA transfers.
D15 to D0
D15 to D0
Address
DACKn
TENDn
WAIT
CKIO
WEn
If a transfer unit is divided into multiple bus cycles and
if CSn is negated during the bus cycle, TEND is also divided.
CSn
RD
T
1
Section 13 Direct Memory Access Controller (DMAC)
T
2
T
aw
Rev. 4.00 Sep. 14, 2005 Page 443 of 982
T
1
T
2
REJ09B0023-0400