HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 342

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
• CS5AWCR
Rev. 4.00 Sep. 14, 2005 Page 292 of 982
REJ09B0023-0400
Bit
5 to 2
1
0
Bit
31 to 19
18
17
16
15 to 13
Bit Name

HW1
HW0
Bit Name

WW2
WW1
WW0

Initial
Value
All 0
0
0
Initial
Value
All 0
0
0
0
All 0
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Delay Cycles from RD, WEn Negation to Address, CSn
Negation
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
read access wait cycles)