HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 557

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HD6417641

Manufacturer Part Number
HD6417641
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
16.6
In master mode, this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 16.22 shows the timing of the bit synchronous circuit and table 16.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
Table 16.4 Time for Monitoring SCL
Note: The pcyc indicates the peripheral clock cycle.
CKS3
0
1
up resistance)
Bit Synchronous Circuit
SCL monitor
timing reference
clock
Internal SCL
Figure 16.22 The Timing of the Bit Synchronous Circuit
SCL
CKS2
0
1
0
1
CKS2CYC
0
1
0
1
0
1
0
1
V
IH
Rev. 4.00 Sep. 14, 2005 Page 507 of 982
Time for Monitoring SCL
6.5 pcyc
5.5 pcyc
18.5 pcyc
17.5 pcyc
16.5 pcyc
15.5 pcyc
40.5 pcyc
39.5 pcyc
Section 16 I
2
C Bus Interface 2 (IIC2)
REJ09B0023-0400

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