HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 987

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RASU/L
CASU/L
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)
RD/WR
DQMxx
CKIO
CKE
CSn
BS
1
2
Note:
t
t
t
t
t
t
RWD1
t
AD1
CSD1
RASD1
AD1
DQMD1
DACD
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
address
Tr
Row
t
t
t
t
t
CASD1
AD1
BSD
RASD1
AD1
TC1
Read command
(High)
t
AD1
TC2
Column
address
t
AD1
Td1
Tc3
t
RDS2
t
t
AD1
t
RDH2
AD1
command
Td2
Tc4
ReadA
(1 to 4)
t
t
BSD
t
CASD1
AD1
Td3
Rev. 4.00 Sep. 14, 2005 Page 937 of 982
Section 25 Electrical Characteristics
Td4
t
RDS2
t
t
t
RDH2
DQMD1
t
CSD1
DACD
Tde
t
t
AD1
RWD1
REJ09B0023-0400