HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 240

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Cache
7.4
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions. The cache is mapped onto the P4 area. The address array is mapped onto
addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to
H'F1FFFFFF. Only longword can be used as the access size for the address array and data array,
and instruction fetches cannot be performed.
7.4.1
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the address, V bit, U bit, and LRU bits to be written to the address array
(figure 7.4 (1)).
In the address field, specify the entry address selecting the entry (bits 11 to 4), W for selecting the
way (bits 13 and 12). A for specifying the existence of associates operation and H'F0 to indicate
address array access (bits 31 to 24). In W (bits 13 and 12), 00 is way 0, 01 is way 1, 10 is way 2,
and 11 is way 3.
7.4.2
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position
within the (16-byte) line, W for selecting the way (bits 13 and 12), and H'F1 to indicate data array
access (bits 31 to 24).
In L (bits 3 and 2), 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3. In
W (bits 13 and 12), 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3. The access size of the
data array is fixed at longword, so specify 00 for bits 1 and 0.
Following two operations are possible for the data array. Information in the address array is not
modified by this operation.
Rev. 4.00 Sep. 14, 2005 Page 190 of 982
REJ09B0023-0400
Memory-Mapped Cache
Address Array
Data Array