HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 530

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 I
16.3.3
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
ICMR is initialized to H'38 by a power-on reset.
Rev. 4.00 Sep. 14, 2005 Page 480 of 982
REJ09B0023-0400
Bit
4
3
2
1
0
Bit
7
6
I
2
Bit Name
SDAOP
SCLO

IICRST

Bit Name
MLS

2
C Bus Mode Register (ICMR)
C Bus Interface 2 (IIC2)
Initial
Value
1
1
1
0
1
Initial
Value
0
0
R/W
R/W
R

R/W

R/W
R/W

Description
SDAO Write Protect
This bit controls change of output level of the SDA pin
by modifying the SDAO bit. To change the output level,
clear SDAO and SDAOP to 0 or set SDAO to 1 and
clear SDAOP to 0. This bit is always read as 1.
This bit monitors SCL output level. When SCLO is 1,
SCL pin outputs high. When SCLO is 0, SCL pin
outputs low.
Reserved
This bit is always read as 1, and cannot be modified.
IIC Control Part Reset
This bit resets the control part except for I
this bit is set to 1 when hang-up occurs because of
communication failure during I
part can be reset without setting ports and initializing
registers.
Reserved
This bit is always read as 1, and cannot be modified.
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Reserved
The write value should always be 0.
2
C bus format is used.
2
C operation, I
2
C registers. If
2
C control