HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 790

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below.
1. The SCIF synchronizes with serial clock input or output and starts the reception.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,
Figure 19.17 shows an example of SCIF receive operation.
Rev. 4.00 Sep. 14, 2005 Page 740 of 982
REJ09B0023-0400
data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this
check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed
(overrun error is detected), further reception is prevented.
the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) or the receive error interrupt enable bit (REIE) in
SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).
Synchronization
Serial data
ORER
clock
RDF
Figure 19.17 Example of SCIF Receive Operation
interrupt
request
RXI
Bit 7
RDF flag cleared
interrupt handler
Data read from
Bit 0
LSB
SCFRDR and
to 0 by RXI
One frame
interrupt
request
MSB
Bit 7
RXI
Bit 0
Bit 1
BRI interrupt request
Bit 6
by overrun error
Bit 7