HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 442

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
(2) Transfer from the normal space interface to the external device with DACK
Notes:
Rev. 4.00 Sep. 14, 2005 Page 392 of 982
REJ09B0023-0400
CSnWCR.WM Setting
1
0
1
0
1
0
1
0
0, 1
1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the
2. Other than the above cases.
3. For single transfer from the external device with DACK to the normal space interface,
4. For single transfer from the normal space interface to the external device with DACK,
DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
32-bit access cycle when the bus width is 16 bits, and the minimum number of idle
cycles between continuous access cycles during 16-byte transfer
the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS,
IWRRD, and IWRRS bits in CSnBCR.
the minimum number of idle cycles is not affected by the DMAIWA and DMAIW bits in
CMNCR.
BSC Register Setting*
CSnBCR Idle Setting
0
0
1
1
2
2
4
4
n (n≥6)
4
Continuous
Transfer*
0
1
1
1
2
2
4
4
n
When Access Size is Less than Bus Width
1
Non-Continuous
Transfer*
3
3
3
3
3
3
4
4
n
2