HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 970

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25 Electrical Characteristics
25.3.2
Table 25.7 Control Signal Timing
Conditions: V
Notes: 1. The RESETP, NMI and IRQ7 to IRQ0 signals are asynchronous signals. When the
Rev. 4.00 Sep. 14, 2005 Page 920 of 982
REJ09B0023-0400
Item
RESETP pulse width
RESETP setup time*
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time*
NMI hold time
IRQ7 to IRQ0 setup time*
IRQ7 to IRQ0 hold time
BACK delay time
STATUS1, STATUS0 delay time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer on time 1
Buss buffer on time 2
2. In standby mode, t
3. In standby mode, t
4. Bcyc indicates external clock cycle time. (B clock cycle)
Control Signal Timing
setup time is satisfied, change of signal level is detected at the rising edge of the clock.
If not, the detection is delayed until the rising edge of the clock.
(100 µs)
must be held low until signals STATUS0 and STATUS1 indicate the reset state (HH).
AV
1
CC
Q = 3.0 V to 3.6 V, V
SS
= 0 V, Ta = −40°C to +85°C
1
1
RESP
RESP
= t
= t
OSC2
OSC2
t
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RESPW
RESPS
RESPH
RESMW
RESMS
RESMH
BREQS
BREQH
NMIS
NMIH
IRQS
IRQH
BACKD
STD
BOFF1
BOFF2
BON1
BON2
CC
(10 ms). When multiplier of the clock is changed, t
(10 ms). When multiplier of the clock is changed, RESETM
= 1.8 V ±5%, AV
Min.
20*
22
2
12*
22
12
1/2t
1/2t
30
30
30
30
—
—
0
0
0
0
2
3
cyc
cyc
Bφ = 50 MHz*
+ 10
+ 10
CC
Max.
—
—
—
—
—
—
—
—
—
—
—
—
1/2t
100
100
100
30
30
= 2.7 V to 3.6 V, V
cyc
2
+ 13 ns
Unit
Bcyc*
ns
ns
Bcyc*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
Figure(s)
25.5, 25.6, 25.9, and
25.10
25.11
25.10
25.11, 25.12
SS
Q = V
SS
REPW
=
= t
PLL1