HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 195

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Clock Pulse Generator (CPG)
The clock pulse generator blocks function as follows:
PLL Circuit 1: PLL circuit 1 doubles, triples, or quadruples, the input clock frequency from the
CKIO pin. The multiplication rate is set by the frequency control register. When this is done, the
phase of the rising edge of the internal clock is controlled so that it will agree with the phase of the
rising edge of the CKIO pin.
PLL Circuit 2: PLL circuit 2 doubles, or quadruples the input clock frequency from the crystal
oscillator or EXTAL pin. The multiplication rate is fixed according to the clock operating mode.
The clock operating mode is specified by the MD0, and MD2 pins. For details on clock operating
mode, see table 4.2.
Crystal Oscillator: The crystal oscillator is an oscillator circuit in which a crystal resonator is
connected to the XTAL pin or EXTAL pin. This can be used according to the clock operating
mode.
Divider: The divider generates a clock signal at the operating frequency used by the internal or
peripheral clock. The operating frequency can be 1, 1/2, 1/3 or 1/4 times the output frequency of
PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division
ratio is set in the frequency control register.
Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
frequency using the MD0, and MD2 pins and the frequency control register.
Standby Control Circuit: The standby control circuit controls the states of the clock pulse
generator and other modules during clock switching or sleep, or standby modes.
Frequency Control Register: The frequency control register has control bits assigned for the
following functions: clock output/non-output from the CKIO pin during standby modes, the
frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal
clock and the peripheral clock.
Standby Control Register: The standby control register has bits for controlling the power-down
modes. See section 6, Power-Down Modes, for more information.
Rev. 4.00 Sep. 14, 2005 Page 145 of 982
REJ09B0023-0400