HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 307

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

6. While the block bit (BL) in the CPU status register (SR) is set to 1, no breaks can be accepted.
11.3.2
1. When L bus/instruction fetch/read/word or longword is set in the break bus cycle register
2. An instruction set for a break before execution breaks when it is confirmed that the instruction
3. When the condition is specified to be occurred after execution, the instruction set with the
 If a logical address issued on the L bus by the CPU is an address to be cached and a cache
 I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by
 The DMAC only issues data access cycles for I bus cycles.
 If a break condition is specified for the I bus, even when the condition matches in an I bus
However, condition determination will be carried out, and if the condition matches, the
corresponding condition match flag is set to 1.
(BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it
breaks before or after the execution of the instruction can then be selected with the PCBA or
PCBB bit of the break control register (BRCR) for the appropriate channel. If an instruction
fetch cycle is set as a break condition, clear LSB in the break address register (BARA or
BARB) to 0. A break cannot be generated as long as this bit is set to 1.
has been fetched and will be executed. This means this feature cannot be used on instructions
fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to
be executed). When this kind of break is set for the delay slot of a delayed branch instruction,
the break is generated prior to execution of the delayed branch instruction.
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delayed branch instruction and its delay slot, a break is not
generated until the first instruction at the branch destination.
Note: If a branch does not occur at a delay condition branch instruction, the subsequent
miss occurs, its bus cycle is issued as a cache fill cycle on the I bus. In this case, it is issued
in longwords and its address is rounded to match longword boundaries. However note that
cache fill is not performed for a write miss in write through mode. In this case, the bus
cycle is issued with the data size specified on the L bus and its address is not rounded. In
write back mode, a write back cycle may be issued in addition to a read fill cycle. It is a
longword bus cycle whose address is rounded to match longword boundaries.
the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are
defined as data access cycles.
cycle resulting from an instruction executed by the CPU, at which instruction the break is
to be accepted cannot be clearly defined.
Break on Instruction Fetch Cycle
instruction is not recognized as a delay slot.
Rev. 4.00 Sep. 14, 2005 Page 257 of 982
Section 11 User Break Controller (UBC)
REJ09B0023-0400