HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 92

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
DSR is assigned as a system register and the following load/store instructions are provided:
When DSR is read by an STS instruction, the upper bits (bits 31 to 8) are all 0.
2.2
2.2.1
Register operands are always longwords (32 bits) (figure 2.9). When the memory operand is only
a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
2.2.2
This LSI has several different data formats that depend on the instruction. This section explains
the data formats for DSP type instructions.
Figure 2.10 shows three DSP-type data formats with different binary point positions. A CPU-type
data format with the binary point to the right of bit 0 is also shown for reference.
The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSP-
type integer format has the binary point between bit 16 and bit 15. The DSP-type logical format
does not have a binary point. The valid data lengths of the data formats depend on the instruction
and the DSP register.
Rev. 4.00 Sep. 14, 2005 Page 42 of 982
REJ09B0023-0400
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
Data Formats
Register Data Format (Non-DSP Type)
DSP-Type Data Formats
31
Figure 2.9 Longword Operand
Longword
0