HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 91

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 2.4
Note: After execution of a PADDC/PSUBC instruction, the DC bit sets the status of the operation
Bits
31 to 8
7
6
5
4
3 to 1
0
result in carry/borrow mode regardless of the CS bits.
Name (Abbreviation)
Reserved bits
Signed Greater Than bit (GT)
Zero bit (Z)
Negative bit (N)
Overflow bit (V)
Condition Select bits (CS)
DSP Condition bit (DC)
DSR Register Bits
Function
0: Always read as 0; always use 0 as the write value
Indicates that the operation result is positive (except 0),
or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is smaller
Indicates that the operation result has overflowed
1: Operation result has overflowed
Designate the mode for selecting the operation result
status to be set in the DC bit
Do not set these bits to 110 or 111
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status has not occurred (false)
1: Designated mode status has occurred
than operand 2
than operand 2
Rev. 4.00 Sep. 14, 2005 Page 41 of 982
REJ09B0023-0400
Section 2 CPU