HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 168

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operation
3.1.9
Data Transfer Operation
This LSI can execute a maximum of two data transfer operations between the DSP register and the
on-chip data memory in parallel for the DSP unit. Three types of data transfer instructions are
provided for the DSP unit.
1. Parallel operation type (using XDB and YDB buses)
2. Double data transfer type (using XDB or YDB buses)
3. Single data transfer type (using LDB bus)
The type 1 instructions execute both DSP data processing and data transfer operations in parallel.
The 32-bit instruction code is used for this type of instruction. Basically, two data transfer
operations can be specified by this type of instruction, but they don't always have to be specified.
One data transfer is for X memory and another is for Y memory. Both of these data transfer
operations cannot be executed for one memory. A load instruction for X memory can specify
either the X0 or X1 register as a destination operand and for a load instruction for Y memory can
specify either the Y0 or Y1 register as a destination operand. Both store operations for X and Y
memories can specify either the A0 or A1 register as a source operand. This type of operation
treats only word data (16 bits). When a word data transfer operation is executed, the upper word of
the register operand is used. In case of word data load, the data is loaded into the upper word of
the destination register, and then the lower side of the destination is automatically cleared.
When a conditional operation is specified as a data processing operation, the specified condition
does not affect any data transfer operations. Figure 3.14 shows this type of data transfer operation
flow.
This type of data transfer operation can access X or Y memory only. Any other memory space
cannot be accessed.
Rev. 4.00 Sep. 14, 2005 Page 118 of 982
REJ09B0023-0400