HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 415

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
1. Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to
CKS0 in RTCSR, and the value set by in RTCOR. The value of bits CKS2 to CKS0 in
RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous
DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in
SDCR, then make the CKS2 to CKS0 and RRC2 to RRC0 settings. When the clock is selected
by bits CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT
value is constantly compared with the RTCOR value, and if the two values are the same, a
refresh request is generated and an auto-refresh is performed for the number of times specified
by the RRC2 to RRC0. At the same time, RTCNT is cleared to zero and the count-up is
restarted. Figure 12.29 shows the auto-refresh cycle timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the
banks to pre-charged state from active state when some bank is being pre-charged. Then REF
command is issued in the Trr cycle after inserting idle cycles of which number is specified by
the WTRP1 and WTRP0 bits in CS3WCR. A new command is not issued for the duration of
the number of cycles specified by the WTRC1 and WTRC0 bits in CS3WCR after the Trr
cycle. The WTRC1 and WTRC0 bits must be set so as to satisfy the SDRAM refreshing cycle
time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the
setting value of the WTRP1 and WTRP0 bits in CS3WCR is longer than or equal to 1 cycle.
Rev. 4.00 Sep. 14, 2005 Page 365 of 982
REJ09B0023-0400