HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 77

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
Figure 2.1 Register Configuration in Each Processing Mode (1)
2. Bank register
3. Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
and indexed GBR indirect addressing mode.
(a) Register configuration for DSP
mode and non_DSP mode (RB = 1)
31
R0_BANK1*
R0_BANK0*
R1_BANK1*
R2_BANK1*
R3_BANK1*
R4_BANK1*
R5_BANK1*
R6_BANK1*
R7_BANK1*
R1_BANK0*
R2_BANK0*
R3_BANK0*
R4_BANK0*
R5_BANK0*
R6_BANK0*
R7_BANK0*
MACH
MACL
GBR
VBR
SPC
SSR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
1
1
, *
, *
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
2
0
(b) Register configuration for DSP
mode and non_DSP mode (RB = 0)
31
Rev. 4.00 Sep. 14, 2005 Page 27 of 982
R0_BANK0*
R0_BANK1*
R1_BANK0*
R2_BANK0*
R3_BANK0*
R4_BANK0*
R5_BANK0*
R6_BANK0*
R7_BANK0*
R1_BANK1*
R2_BANK1*
R3_BANK1*
R4_BANK1*
R5_BANK1*
R6_BANK1*
R7_BANK1*
MACH
MACL
GBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
1
1
, *
, *
3
3
3
3
3
3
3
2
2
2
2
2
2
2
3
2
REJ09B0023-0400
0
Section 2 CPU