HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 316

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 User Break Controller (UBC)
Break Condition Specified for I Bus Data Access Cycle:
(Example 3-1)
• Register specifications
11.4
1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the
2. UBC cannot monitor access to the L bus and I bus in the same channel.
3. Note on specification of sequential break:
Rev. 4.00 Sep. 14, 2005 Page 266 of 982
REJ09B0023-0400
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00007878, BDMRB = H'00000F0F,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Bus cycle: I bus/instruction fetch/read (operand size is not included in the condition)
<Channel B>
Address:
Data:
Bus cycle: I bus/data access/write/byte
On channel A, a user break occurs when instruction fetch is performed for address H'00314156
in the memory space.
On channel B, a user break occurs when the I bus writes byte data H'7* in address
H'00055555.
period from executing an instruction to rewrite the UBC register till the new value is actually
rewritten, the desired break may not occur. In order to know the timing when the UBC register
is changed, read from the last written register. Instructions after then are valid for the newly
written register value.
A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel
match occurs in another bus cycle in sequential break setting. Therefore, no break occurs even
if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is
set.
Usage Notes
H'00314156, Address mask: H'00000000
H'00055555, Address mask: H'00000000
H'00000078, Data mask: H'0000000F