HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 124

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 74 of 982
REJ09B0023-0400
Instruction
DMULU.L Rm,Rn
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
@Rm+,@Rn+
@Rm+,@Rn+
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Instruction Code
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
Operation
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 4 bits
Rn – 1 → Rn, if Rn = 0, 1
→ T, else 0 → T
A byte in Rm is sign-extended
→ Rn
A word in Rm is sign-extended
→ Rn
A byte in Rm is zero-extended
→ Rn
A word in Rm is zero-extended
→ Rn
Signed operation of (Rn)
× (Rm) → MAC → MAC,
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
Signed operation of (Rn)
× (Rm) → MAC → MAC,
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
Rn × Rm → MACL
32 × 32 → 32 bits
Signed operation of
Rn × Rm → MAC
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32 bits
0–Rm → Rn
0–Rm–T → Rn,
Borrow → T
Rn–Rm → Rn
Rn–Rm–T → Rn,
Borrow → T
Execution
States
2(5) *
1
1
1
1
1
2(5)*
2(5)*
2(5)*
1(3)*
1(3)*
1
1
1
1
1
1
1
2
2
1
T Bit
—
Comparison
result
—
—
—
—
—
—
—
—
—
—
Borrow
—
Borrow