HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 29

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Figures
Section 1 Overview
Figure 1.1 Block Diagram .............................................................................................................. 7
Figure 1.2 Pin Assignments (BGA-256)......................................................................................... 8
Section 2 CPU
Figure 2.1 Register Configuration in Each Processing Mode (1) ................................................. 27
Figure 2.2 Register Configuration in Each Processing Mode (2) ................................................. 28
Figure 2.3 General Registers (Not in DSP Mode) ........................................................................ 29
Figure 2.4 General Registers (DSP Mode) ................................................................................... 30
Figure 2.5 Control Registers (1) ................................................................................................... 33
Figure 2.5 Control Registers (2) ................................................................................................... 34
Figure 2.6 System Registers ......................................................................................................... 35
Figure 2.7 DSP Registers.............................................................................................................. 39
Figure 2.8 Connections of DSP Registers and Buses ................................................................... 39
Figure 2.9 Longword Operand...................................................................................................... 42
Figure 2.10 Data Formats ............................................................................................................. 43
Figure 2.11 Byte, Word, and Longword Alignment ..................................................................... 44
Figure 2.12 X and Y Data Transfer Addressing ........................................................................... 53
Figure 2.13 Single Data Transfer Addressing............................................................................... 54
Figure 2.14 Modulo Addressing ................................................................................................... 55
Figure 2.15 DSP Instruction Formats ........................................................................................... 61
Figure 2.16 Sample Parallel Instruction Program......................................................................... 89
Figure 2.17 Examples of Conditional Operations and Data Transfer Instructions ....................... 97
Section 3 DSP Operation
Figure 3.1 ALU Fixed-Point Arithmetic Operation Flow............................................................. 99
Figure 3.2 Operation Sequence Example.................................................................................... 101
Figure 3.3 DC Bit Generation Examples in Carry or Borrow Mode .......................................... 101
Figure 3.4 DC Bit Generation Examples in Negative Value Mode ............................................ 102
Figure 3.5 DC Bit Generation Examples in Overflow Mode...................................................... 102
Figure 3.6 ALU Integer Arithmetic Operation Flow .................................................................. 104
Figure 3.7 ALU Logical Operation Flow ................................................................................... 106
Figure 3.8 Fixed-Point Multiply Operation Flow ....................................................................... 107
Figure 3.9 Arithmetic Shift Operation Flow............................................................................... 109
Figure 3.10 Logical Shift Operation Flow.................................................................................. 111
Figure 3.11 PDMSB Operation Flow ......................................................................................... 113
Figure 3.12 Rounding Operation Flow ....................................................................................... 116
Figure 3.13 Definition of Rounding Operation........................................................................... 116
Rev. 4.00 Sep. 14, 2005 Page xxix of l