HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 200

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Clock Pulse Generator (CPG)
Rev. 4.00 Sep. 14, 2005 Page 150 of 982
REJ09B0023-0400
Bit
11, 10
9
8
7, 6
5
4
3, 2
1
0
Bit Name

STC1
STC0

IFC1
IFC0

PFC1
PFC0
Initial
Value
All 0
0
0
All 0
0
0
All 0
1
1
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Frequency multiplication ratio of PLL circuit 1
00: × 1 time
01: × 2 times
10: × 3 times
11: × 4 times
Reserved
These bits are always read as 0. The write value
should always be 0.
Internal Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
Reserved
These bits are always read as 0. The write value
should always be 0.
Peripheral Clock Frequency Division Ratio
These bits specify the division ratio of the peripheral
clock frequency with respect to the output frequency
of PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time