HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 519

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

15.4.2
Table 15.4 Reset Configuration
Notes: 1. Performs normal mode and ASE mode settings
15.4.3
The timing of data output from the TDO is switched by the command type set in the SDIR. The
timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,
SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.
When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are
set, TDO is output at the TCK rising edge earlier than the JTAG standard by a half cycle.
ASEMD0*
H
L
2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RESETP pin
Reset Configuration
TDO Output Timing
1
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
Another RESETP assert (power-on reset)
is negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI
operation is enabled, but the CPU does not start up. The reset hold state is cancelled
by the following:
RESETP
L
H
L
H
TRST
L
H
L
H
L
H
L
H
Chip State
Normal reset and H-UDI reset
Normal reset
H-UDI reset only
Normal operation
Reset hold*
Normal reset
H-UDI reset only
Normal operation
Section 15 User Debugging Interface (H-UDI)
Rev. 4.00 Sep. 14, 2005 Page 469 of 982
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