HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 407

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Single Write: A write access ends in one cycle when data is written in non-cacheable region and
the data bus width is larger than or equal to access size.
Figure 12.22 shows the single write basic timing.
RASL, RASU
CASL, CASU
Figure 12.22 Single Write Basic Timing (Auto-Precharge)
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CSn
BS
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tr
Tc1
Trwl
Tap
Rev. 4.00 Sep. 14, 2005 Page 357 of 982
Section 12 Bus State Controller (BSC)
REJ09B0023-0400