HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 621

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

18.4.3
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 18.29 shows the register combinations used in buffer operation.
Table 18.29 Register Combinations in Buffer Operation
• When TGR is an output compare register
Channel
0
3
4
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 18.13.
Buffer Operation
register
Buffer
Figure 18.13 Compare Match Buffer Operation
Timer General Register
TGRA_0
TGRB_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Compare match signal
Timer general
register
Section 18 Multi-Function Timer Pulse Unit (MTU)
Comparator
Rev. 4.00 Sep. 14, 2005 Page 571 of 982
Buffer Register
TGRC_0
TGRD_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TCNT
REJ09B0023-0400