HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 466

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Direct Memory Access Controller (DMAC)
13.3.5
The DMA operation register (DMAOR) is a 32-bit read/write register that specifies the priority
level of channels at the DMA transfer. This register shows the DMA transfer status. The DMAOR
is initialized to H'00000000 at reset and retains the current value in the standby or module standby
mode.
Rev. 4.00 Sep. 14, 2005 Page 416 of 982
REJ09B0023-0400
Bit
31, 30
29
28
27, 26
DMA Operation Register (DMAOR)
Bit Name

CMS1
CMS0

Initial
Value
All 0
0
0
All 0
R/W
R
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cycle Steal Mode Select 1, 0
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Reserved (Setting prohibited)
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value
should always be 0.
Executes one DMA transfer in each of 16 clocks of
an external bus clock.
Executes one DMA transfer in each of 64 clocks of
an external bus clock.