HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 776

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Serial Communication Interface with FIFO (SCIF)
Figure 19.3 shows a sample flowchart for initializing the SCIF.
Rev. 4.00 Sep. 14, 2005 Page 726 of 982
REJ09B0023-0400
After reading BRK, DR, and ER flags
in SCFSR, and each flag in SCLSR,
Clear TE and RE bits in SCSCR to 0
Set TE and RE bits in SCSCR to 1,
Set data transfer format in SCSMR
in SCSCR (leaving TE, RE, TIE,
Set RTRG1-0 and TTRG1-0 bits
and set TIE, RIE, and REIE bits
in SCFCR, and clear TFRST
Set TFRST and RFRST bits
Set CKE1 and CKE0 bits
and RIE bits cleared to 0)
1-bit interval elapsed?
Figure 19.3 Sample Flowchart for SCIF Initialization
write 0 to clear them
Set value in SCBRR
and RFRST bits to 0
Start of initialization
End of initialization
in SCFCR to 1
Wait
Yes
No
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.