HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 250

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Exception Handling
9.2
9.2.1
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. The return from exception handler (RTE)
instruction is issued by the exception handler routine on completion of the routine, restoring the
contents of PC and SR to return to the processor state at the point of interruption and the address
where the exception occurred.
A basic exception handling sequence consists of the following operations. If an exception occurs
and the CPU accepts it, operations 1 to 8 are executed.
1. The contents of PC is saved in SPC.
2. The contents of SR is saved in SSR.
3. The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
4. The register bank (RB) bit in SR is set to 1.
5. An exception code identifying the exception event is written to bits 11 to 0 of the exception
6. If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA
7. Instruction execution jumps to the designated exception vector address to invoke the handler
The above operations from 1 to 7 are executed in sequence. During these operations, no other
exceptions may be accepted unless multiple exception acceptance is enabled.
In an exception handling routine for a general exception, the appropriate exception handling must
be executed based on an exception source determined by the EXPEVP. In an interrupt exception
handling routine, the appropriate exception handling must be executed based on an exception
source determined by the INTEVT2. After the exception handling routine has been completed,
program execution can be resumed by executing an RTE instruction. The RTE instruction causes
the following operations to be executed.
1. The contents of the SSR are restored into the SR to return to the processing state in effect
2. A delay slot instruction of the RTE instruction is executed.
3. Control is passed to the address stored in the SPC.
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event (EXPEVT) or interrupt event (INTEVT2) register.
instruction is set to TRA.
routine.
before the exception handling took place.
Exception Handling Function
Exception Handling Flow