HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 809

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1)
USBEPSZ1 indicates, in bytes, the amount of data received from the host by endpoint 1. The
endpoint 1 FIFO buffer has a dual-FIFO configuration. The receive data size indicated by this
register refers to the currently selected FIFO (that can be read by CPU).
USBEPSZ1 can be initialized to H'00 by a power-on reset.
20.3.17 USB Trigger Register (USBTRG)
USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint.
USBTRG can be initialized to H'00 by a power-on reset.
Bit
7 to 0
Bit
7
6
5
4
3
Bit Name

Bit Name

EP3PKTE
EP1RDFN
EP2PKTE

Initial
Value
All 0
Initial
Value
0
0
0
0
0
R/W
R
R/W
R
W
W
W
R
Description
Number of bytes received by endpoint 1
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-FIFO configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.
EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 FIFO buffer, the transmit data is fixed by
writing 1 to this bit.
Reserved
The write value should always be 0.
Rev. 4.00 Sep. 14, 2005 Page 759 of 982
Section 20 USB Function Module
REJ09B0023-0400