HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 328

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Bus State Controller (BSC)
• Refresh timer control/status register (RTCSR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
• Reset wait counter (RWTCNT)
12.4.1
CMNCR is a 32-bit register that controls the common items for each area. This register is only
initialized by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Do not access external memory other than area 0 until the CMNCR register initialization is
complete.
Rev. 4.00 Sep. 14, 2005 Page 278 of 982
REJ09B0023-0400
Bit
31 to 16
15
14, 13
12
Common Control Register (CMNCR)
Bit Name

WAITSEL

MAP
Initial
Value
All 0
0
All 0
0
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
WAIT Signal Sampling Timing Specification
Specifies the external WAIT signal sampling timing.
0: Samples the WAIT signal at the falling edge of the
1: Samples the WAIT signal at the rising edge of the
Reserved
These bits are always read as 0. The write value
should always be 0.
Space Specification
Selects the address map for the external address
space. The address maps to be selected are shown in
tables 12.2 and 12.3.
0: Selects address map 1.
1: Selects address map 2.
CKIO. In this case, the WAIT signal can be input
asynchronously.
CKIO. In this case, the WAIT signal must be input
synchronously.