HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 238

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Cache
7.3.2
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. LRU
is updated so that the hit way is the latest.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced follows table
7.5. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss
is loaded from external memory to the cache, the instruction or data is transferred to the CPU in
parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0 and
the V bit is set to 1. LRU is updated so that the replaced way becomes the latest. When the U bit
of the entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle
starts after the entry is transferred to the write-back buffer. After the cache completes its update
cycle, the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes.
7.3.3
Prefetch Hit: LRU is updated so that the hit way becomes the latest. The contents in other caches
are not modified. No instructions or data is transferred to the CPU.
Prefetch Miss: No instructions or data is transferred to the CPU. The way to be replaced follows
table 7.4. Other operations are the same in case of read miss.
7.3.4
Write Hit: In a write access in write-back mode, the data is written to the cache and no external
memory write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that
the hit way becomes the latest. In write-through mode, the data is written to the cache and an
external memory write cycle is issued. The U bit of the written entry is not updated and LRU is
updated so that the replaced way becomes the latest.
Write Miss: In write-back mode, an external bus cycle starts when a write miss occurs, and the
entry is updated. The way to be replaced follows table 7.5. When the U bit of the entry to be
replaced is 1, the cache update cycle starts after the entry is transferred to the write-back buffer.
The write-back unit is 16 bytes. Data is written to the cache and the U bit is set to 1. V bit is set to
1. LRU is updated so that the replaced way becomes the latest. After the cache completes its
update cycle, the write-back buffer writes the entry back to the memory. In write-through mode,
no write to cache occurs in a write miss; the write is only to the external memory.
Rev. 4.00 Sep. 14, 2005 Page 188 of 982
REJ09B0023-0400
Read Access
Prefetch Operation
Write Access