HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 546

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 I
16.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and bits CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If eighth receive clock pulse falls while RDRF is 1, SCL
4. The last byte data is read by reading ICDRR.
Rev. 4.00 Sep. 14, 2005 Page 496 of 982
REJ09B0023-0400
(Master output)
(Master output)
in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the
ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read).
(Since the read data show the slave address and R/W, it is not used.)
is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
(Slave output)
(Slave output)
processing
ICDRR
ICDRS
RDRF
SCL
SDA
SDA
User
SCL
Slave Receive Operation
2
C Bus Interface 2 (IIC2)
Figure 16.11 Slave Receive Mode Operation Timing (1)
[2] Read ICDRR (dummy read)
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
[2] Read ICDRR
A
9
Bit 7
Data 1
1
Data 2