HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 757

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

19.3.8
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in three
channels.
The SCBRR setting is calculated as follows:
• Asynchronous mode:
• Synchronous mode:
Table 19.2 SCSMR Settings
Note: The bit rate error in asynchronous is given by the following formula:
n
0
1
2
3
N =
N =
B:
N:
Pφ: Operating frequency for peripheral modules (MHz)
n:
Error (%) =
Bit Rate Register (SCBRR)
8 × 2
64 × 2
Bit rate (bits/s)
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 19.2.)
Pφ
Pφ
2n-1
2n-1
× B
(N + 1) × B × 64
× B
Clock Source
Pφ
Pφ/4
Pφ/16
Pφ/64
× 10
× 10
Pφ × 10
6
6
- 1
- 1
6
2n-1
× 2
Section 19 Serial Communication Interface with FIFO (SCIF)
- 1
CKS1
0
0
1
1
× 100
Rev. 4.00 Sep. 14, 2005 Page 707 of 982
SCSMR Settings
CKS0
0
1
0
1
REJ09B0023-0400