HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 301

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

11.2.9
BRCR sets the following conditions:
1. Channels A and B are used in two independent channel conditions or under the sequential
2. A break is set before or after instruction execution.
3. Specify whether to include the number of execution times on channel B in comparison
4. Determine whether to include data bus on channel B in comparison conditions.
5. Enable PC trace.
The break control register (BRCR) is a 32-bit readable/writable register that has break conditions
match flags and bits for setting a variety of break conditions.
Bit
31 to 16
15
14
condition.
conditions.
Break Control Register (BRCR)
Bit Name

SCMFCA
SCMFCB
Initial
Value
All 0
0
0
R/W
R
R/W
R/W
L Bus Cycle Condition Match Flag A
L Bus Cycle Condition Match Flag B
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
When the L bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1 (not
cleared to 0). In order to clear this flag, write 0 into this
bit.
0: The L bus cycle condition for channel A does not
1: The L bus cycle condition for channel A matches
When the L bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1 (not
cleared to 0). In order to clear this flag, write 0 into this
bit.
0: The L bus cycle condition for channel B does not
1: The L bus cycle condition for channel B matches
match
match
Rev. 4.00 Sep. 14, 2005 Page 251 of 982
Section 11 User Break Controller (UBC)
REJ09B0023-0400