HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 206

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Watchdog Timer (WDT)
Figure 5.1 shows a block diagram of the WDT.
5.2
The WDT has the following two registers. See section 24, List of Registers, for the addresses and
access sizes of these registers.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
5.2.1
The watchdog timer counter (WTCNT) is an 8-bit readable/writable register that is incremented by
cycles of the selected clock signal. When an overflow occurs, it generates a reset in watchdog
timer mode and an interrupt in interval timer mode. The WTCNT counter is initialized to H'00
only by a power-on reset caused by the RESETP pin. Use a word access to write to the WTCNT
counter, writing H'5A in the upper byte. Use a byte access to read the WTCNT.
Note: The WTCNT differs from other registers in the prevention of erroneous writes.
Rev. 4.00 Sep. 14, 2005 Page 156 of 982
REJ09B0023-0400
See section 5.2.3, Notes on Register Access, for details.
Register Descriptions
Watchdog Timer Counter (WTCNT)
cancellation
[Legend]
WTCSR:
WTCNT:
Interrupt
Standby
Internal
request
request
reset
Watchdog timer control/status register
Watchdog timer counter
Standby
Interrupt
Figure 5.1 Block Diagram of the WDT
control
control
control
Reset
WTCSR
Clock selection
Overflow
Bus interface
WDT
WTCNT
Clock selector
Divider
Clock
Standby
mode
Peripheral
clock