HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 419

• Manufacturer Part Number: HD6417641
• Manufacturer: RENESAS [Renesas Technology Corp]

RASL, RASU
CASL, CASU
Power-Down Mode: If the PDOWN bit in the SDCR register is set to 1, the SDRAM is placed in
the power-down mode by bringing the CKE signal to the low level in the non-access cycle. This
power-down mode can effectively lower the power consumption in the non-access cycle.
However, please note that if an access occurs in the power-down mode, a cycle of overhead occurs
because a cycle is needed to assert the CKE in order to cancel the power-down mode.
Figure 12.32 shows the access timing in the power-down mode.
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CKE
CSn
BS
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tr
Figure 12.31 Low-Frequency Mode Access Timing
Tc1
Td1
Tde
Tap
(High)
Tr
Rev. 4.00 Sep. 14, 2005 Page 369 of 982
Tc1
Section 12 Bus State Controller (BSC)
Tnop
Trwl
REJ09B0023-0400
Tap